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TMS320F28335ZHHA 参数 Datasheet PDF下载

TMS320F28335ZHHA图片预览
型号: TMS320F28335ZHHA
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
SPRS439IJUNE 2007REVISED MARCH 2011  
www.ti.com  
6.9.2 GPIO - Input Timing  
(A)  
GPIO Signal  
GPxQSELn = 1,0 (6 samples)  
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined  
by GPxCTRL[QUALPRD]  
w(SP)  
(B)  
t
w(IQSW)  
(C)  
(SYSCLKOUT cycle * 2 * QUALPRD) * 5  
)
Sampling Window  
SYSCLKOUT  
QUALPRD = 1  
(SYSCLKOUT/2)  
(D)  
Output From  
Qualifier  
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It  
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value  
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin  
will be sampled).  
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.  
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is  
used.  
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or  
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure  
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide  
pulse ensures reliable recognition.  
Figure 6-10. Sampling Mode  
Table 6-13. General-Purpose Input Timing Requirements  
MIN  
1tc(SCO)  
MAX  
UNIT  
cycles  
cycles  
cycles  
cycles  
cycles  
QUALPRD = 0  
tw(SP)  
Sampling period  
QUALPRD 0  
2tc(SCO) * QUALPRD  
tw(SP) * (n(1) – 1)  
2tc(SCO)  
tw(IQSW)  
Input qualifier sampling window  
Pulse duration, GPIO low/high  
Synchronous mode  
With input qualifier  
(2)  
tw(GPI)  
tw(IQSW) + tw(SP) + 1tc(SCO)  
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.  
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.  
132  
Electrical Specifications  
Copyright © 2007–2011, Texas Instruments Incorporated  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232