TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
6.7 Clock Requirements and Characteristics
Table 6-6. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
MIN
20
20
4
TYP
MAX UNIT
35
Crystal (X1/X2)
35
MHz
150
fx
Input clock frequency
150-MHz device
100-MHz device
External oscillator/clock
source (XCLKIN or X1 pin)
4
100
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1 - 5
MHz
Table 6-7. XCLKIN Timing Requirements – PLL Enabled
NO.
C8
MIN
MAX UNIT
tc(CI)
tf(CI)
Cycle time, XCLKIN
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
33.3
200
6
ns
ns
ns
%
C9
C10 tr(CI)
6
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(CI)
Pulse duration, XCLKIN high as a percentage of tc(CI)
45
45
55
55
(1)
%
(1) This applies to the X1 pin also.
Table 6-8. XCLKIN Timing Requirements – PLL Disabled
NO.
MIN
6.67
10
MAX UNIT
150-MHz device
250
ns
C8
tc(CI)
Cycle time, XCLKIN
100-MHz device
Up to 30 MHz
250
6
C9
tf(CI)
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
ns
2
30 MHz to 150 MHz
Up to 30 MHz
6
C10 tr(CI)
ns
2
30 MHz to 150 MHz
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(CI)
Pulse duration, XCLKIN high as a percentage of tc(CI)
45
45
55
55
%
%
(1)
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 3-19.
Table 6-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)
NO.
PARAMETER
Cycle time, XCLKOUT
MIN
6.67
10
TYP
MAX UNIT
150-MHz device
100-MHz device
C1
tc(XCO)
ns
C3
C4
C5
C6
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
Fall time, XCLKOUT
2
2
ns
ns
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H – 2
H – 2
H + 2
ns
ns
H + 2
(3)
131072tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
127
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