TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439I–JUNE 2007–REVISED MARCH 2011
Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(Changed CPU Frequency)
(PLL Lock-up Time, t ) is
p
131072 OSCCLK Cycles Long.)
Figure 6-8. Example of Effect of Writing Into PLLCR Register
6.9 General-Purpose Input/Output (GPIO)
6.9.1 GPIO - Output Timing
Table 6-12. General-Purpose Output Switching Characteristics
PARAMETER
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
8
ns
25
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-9. General-Purpose Output Timing
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
131
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