TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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6.9.4 Low-Power Mode Wakeup Timing
Table 6-14 shows the timing requirements, Table 6-15 shows the switching characteristics, and
Figure 6-12 shows the timing diagram for IDLE mode.
Table 6-14. IDLE Mode Timing Requirements(1)
MIN NOM
2tc(SCO)
5tc(SCO) + tw(IQSW)
MAX
UNIT
Without input qualifier
With input qualifier
Pulse duration, external wake-up
signal
tw(WAKE-INT)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-15. IDLE Mode Switching Characteristics(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, external wake signal to
(2)
program execution resume
Wake-up from Flash
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
20tc(SCO) + tw(IQSW)
1050tc(SCO)
cycles
cycles
cycles
•
Flash module in active state
td(WAKE-IDLE)
Wake-up from Flash
•
•
Flash module in sleep state
Wake-up from SARAM
1050tc(SCO) + tw(IQSW)
20tc(SCO)
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)(B)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-12. IDLE Entry and Exit Timing
134
Electrical Specifications
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