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TMS320TCI6487 参数 Datasheet PDF下载

TMS320TCI6487图片预览
型号: TMS320TCI6487
PDF下载: 下载PDF文件 查看货源
内容描述: 通信基础设施数字信号处理器 [Communications Infrastructure Digital Signal Processor]
分类和应用: 数字信号处理器通信
文件页数/大小: 206 页 / 2183 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320TCI6487  
TMS320TCI6488  
Communications Infrastructure Digital Signal Processor  
SPRS358FAPRIL 2007REVISED AUGUST 2008  
www.ti.com  
After device reset, all peripherals on the TCI6487/8 device are in a disabled state and must be enabled by  
software before being used. It is possible to enable only the peripherals needed by the application while  
keeping the rest disabled. Note that peripherals in a disabled state are held in reset with their clocks  
gated. For more information on how to enable peripherals, see Section 3.2, Peripheral Selection After  
Device Reset.  
Peripherals used for booting, like I2C, are automatically enabled after device reset. It is possible to disable  
peripherals used for booting after the boot process is complete. This, too, results in gating of the clock(s)  
to the powered-down peripheral. Once a peripheral is powered-down, it must remain powered down until  
the next device reset.  
The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+  
Megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or  
the entire C64x+ Megamodule through the power-down controller based on its own execution thread or in  
response to an external stimulus from a host or global controller. More information on the power-down  
features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide  
(literature number SPRU871).  
8.3.4 SmartReflex  
Increasing the device complexity increases its power consumption and with the smaller transistor  
structures responsible for higher achievable clock rates and increased performance, comes an inevitable  
penalty, increasing the leakage currents. Leakage currents are present in any active circuit, independently  
of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type  
and process technology. Higher clock rates also increase dynamic power, the power used when  
transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O  
activity.  
Texas Instruments' SmartReflex™ technology is used to decrease both static and dynamic power  
consumption while maintaining the device performance. SmartReflex in the TMS320TCI6487/8 device is a  
feature that allows the core voltage to be optimized based on the process corner of the device. This  
requires a voltage regulator for each TCI6487/8 device.  
To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is  
implemented whenever the TCI6487/8 is used.  
The voltage selection is done using 4 VCNTL pins which are used to select the output voltage of the core  
voltage regulator. For complete information on SmartReflex, see the TMS320TCI6488 Hardware Design  
Guide application report (literature number SPRAAG5).  
78  
Peripheral Information and Electrical Specifications  
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