TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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8.4.1 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move
data between system memories. DMA channels can be triggered by synchronization events generated by
system peripherals. Table 8-2 lists the source of the synchronization event associated with each of the
DMA channels. The association of each synchronization event and DMA channel is fixed and cannot be
reprogrammed. Additional events are available to the EDMA3 via an external interrupt controller. For more
details on Chip Interrupt Controller 3 (CIC3), see Section 8.5.2.
Table 8-2. EDMA3 Channel Synchronization Events(1)
EVENT CHANNEL
EVENT
TINT0L
EVENT DESCRIPTION
0
Timer Interrupt Low
Timer Interrupt High
Timer Interrupt Low
Timer Interrupt High
Timer Interrupt Low
Timer Interrupt High
1
TINT0H
2
TINT1L
3
TINT1H
4
TINT2L
5
TINT2H
6
CIC3_EVT0
CIC3_EVT1
CIC3_EVT2
CIC3_EVT3
CIC3_EVT4
CIC3_EVT5
XEVT0
CIC_EVT_o [0] from Chip Interrupt Controller
CIC_EVT_o [1] from Chip Interrupt Controller
CIC_EVT_o [2] from Chip Interrupt Controller
CIC_EVT_o [3] from Chip Interrupt Controller
CIC_EVT_o [4] from Chip Interrupt Controller
CIC_EVT_o [5] from Chip Interrupt Controller
McBSP 0 Transmit Event
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
REVT0
McBSP 0 Receive Event
XEVT1
McBSP 1 Transmit Event
REVT1
McBSP 1Receive Event
FSEVT4
FSEVT5
FSEVT6
FSEVT7
FSEVT8
FSEVT9
FSEVT10
FSEVT11
FSEVT12
FSEVT13
CIC3_EVT6
CIC3_EVT7
VCPREVT
VCPXEVT
TCPREVT
TCPXEVT
SEMINT0
SEMINT1
SEMINT2
-
Frame Synchronization Event 4
Frame Synchronization Event 5
Frame Synchronization Event 6
Frame Synchronization Event 7
Frame Synchronization Event 8
Frame Synchronization Event 9
Frame Synchronization Event 10
Frame Synchronization Event 11
Frame Synchronization Event 12
Frame Synchronization Event 13
CIC_EVT_o [6] from Chip Interrupt Controller
CIC_EVT_o [7] from Chip Interrupt Controller
VCP Receive Event
VCP Transmit Event
TCP Receive Event
TCP Transmit Event
Semaphore Interrupt 0
Semaphore Interrupt 1
Semaphore Interrupt 2
Reserved
AIF_EVT0
AIF_EVT1
AIF CPU Interrupt 0
AIF CPU Interrupt 1
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the manual event set or transfer
completion events.
80
Peripheral Information and Electrical Specifications
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