TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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7.2 Recommended Operating Conditions(1)(2)
MIN
CVDD - (0.03CVDD
NOM
MAX UNIT
CVDD
Supply core voltage (scalable)
1.1-V supply core I/O voltage
1.8-V supply I/O voltage
)
0.9 - 1.2 CVDD + (0.03CVDD
)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DVDD11
1.045
1.71
1.1
1.155
DVDD18
1.8
1.89
0.51 * DVDD18
1.155
VREFSSTL
AIF_VDDA11
AIF_VDDD11
AIF_VDDR18
AIF_VDDT11
DDR2 reference voltage
0.49 * DVDD18
1.045
0.5 * DVDD18
AIF SERDES analog supply
AIF SERDES digital supply
AIF SERDES regulator supply
AIF SERDES termination supply
1.1
1.1
1.8
1.1
1.1
1.1
1.8
1.1
1.8
1.8
0
1.045
1.155
1.71
1.89
1.045
1.155
SGR_VDDA11 SRIO/SGMII SERDES analog supply
SGR_VDDD11 SRIO/SGMII SERDES digital supply
SGR_VDDR18 SRIO/SGMII SERDES regulator supply
SGR_VDDT11 SRIO/SGMII SERDES termination supply
1.045
1.155
1.045
1.155
1.71
1.89
1.045
1.155
AVDD118
AVDD218
VSS
PLL1 analog supply
PLL2 analog supply
Ground
1.71
1.89
1.71
1.89
0
0
LVCMOS
0.65 * DVDD18
I2C/VCNTL,
SmartReflex
VIH
High-level input voltage(3)
0.7 * DVDD18
V
DDR2 EMIF
LVCMOS
VREFSSTL + 0.125
DVDD18 + 0.3
0.35 * DVDD18
VREFSSTL - 0.1
0.3 * DVDD18
V
V
V
V
VIL
TC
Low-level input voltage(3)
DDR2 EMIF
I2C/VCNTL
-0.3
0
Operating case temperature
100 °C
(1) A heatsink and implementation of the SmartReflex solution is required for proper device operation. For more details on SmartReflex, see
Section 8.3.4.
(2) All SERDES I/Os comply with the XAUI Electical Specification, IEEE 802.3ae-2002.
(3) All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI
Electical Specification, IEEE 802.3ae-2002.
74
Device Operating Conditions
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