TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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8.10.3 I2C Electrical Data/Timing
Table 8-37. Timing Requirements for I2C Timings(1)
(see Figure 8-26)
NO.
STANDARD MODE
FAST MODE
UNIT
MIN
10
MAX
MIN
2.5
MAX
1
2
tc(SCL)
Cycle time, SCL
µs
µs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
0.6
3
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
4
0.6
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
µs
µs
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SDLH)
th(SDA-SDLL)
Setup time, SDA valid before SCL high
250
0(3)
Hold time, SDA valid after SCL low (for I2C
bus™ devices)
0
0.9(4)
8
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions.
4.7
1.3
µs
9
tr(SDA)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
10
11
12
13
tr(SCL)
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
0.6
tf(SDA)
tf(SCL)
300
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for
STOP condition)
4
14
15
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50
ns
(5)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement, tsu(SDA-SCLH)≥ 250 ns, must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line, Tr max + Tsu(SDA-SCLH) = 1000 + 250 + 1250 ns
(according to the standard-mode I2C-bus specification), before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum, th(SDA-SCLL), has only to be met if the device does not stretch the low period, tw(SCLL), of the SCL signal.
(5) Cb = total capacitance of one bus line, in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 8-26. I2C Receive Timings
136
Peripheral Information and Electrical Specifications
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