TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.10.2 I2C Peripheral Register Description(s)
The memory map of the I2C is shown in Table 8-36.
Table 8-36. I2C Registers
HEX ADDRESS
02B0 4000
ACRONYM
REGISTER NAME
ICOAR
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
ICPID1
ICPID2
-
I2C Own Address Register
02B0 4004
I2C Interrupt Mask/Status Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
02B0 4008
02B0 400C
02B0 4010
02B0 4014
02B0 4018
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
02B0 401C
02B0 4020
02B0 4024
02B0 4028
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
02B0 402C
02B0 4030
02B0 4034
I2C Peripheral Identification Register 1 [Value: 0x0000 0105]
I2C Peripheral Identification Register 2 [Value: 0x0000 0005]
Reserved
02B0 4038
02B0 403C - 02B0 405C
02B0 4060 - 02B0 407F
02B0 4080 - 02B3 FFFF
-
Reserved
-
Reserved
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Peripheral Information and Electrical Specifications
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