TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
Even
register
file A
(A0, A2,
A4...A30)
src1
Odd
register
fileA
(A1, A3,
A5...A31)
.L1
src2
odd dst
even dst
long src
(D)
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
Datapath A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
.D1
.D2
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
DA1
DA2
2x
1x
Even
register
file B
(B0, B2,
B4...B30)
Odd
register
file B
(B1, B3,
B5...B31)
src2
src1
dst
32 LSB
32 MSB
LD2a
LD2b
src2
(C)
.M2
.S2
src1
dst2
dst1
32
32
(B)
(A)
src2
src1
odd dst
even dst
long src
(D)
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
odd dst
src2
.L2
src1
Control Register
A. On .M unit, dst2 is 32 MB.
B. On .M unit, dst1 is 32 LSB.
C. On 64x+ CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+TM CPU (DSP Core) Data Path
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