TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
Table 2-2. Memory Map Summary (continued)
HEX ADDRESS RANGE
MEMORY BLOCK DESCRIPTION
SYMMETRIC L2
ASYMMETRIC L2
SIZE
C64x+
MEGAMODULE
CORE 0
C64x+
MEGAMODULE
CORE 1
C64x+
MEGAMODULE
CORE 2
C64x+
MEGAMODULE
CORE 0
C64x+
MEGAMODULE
CORE 1
C64x+
MEGAMODULE
CORE 2
START
END
0295 0040
0296 0000
0296 0040
029A 0000
029A 0200
029C 0000
029C 0200
02A0 0000
02A0 8000
02A2 0000
02A2 8000
02A3 0000
02A3 8000
02A4 0000
02A4 8000
02A5 0000
02A8 0000
02A8 0100
02AC 0000
02AC 1000
02AC 4000
02AC 4100
02AD 0000
02AD 8000
02AE 0000
02AE 8000
02B0 0000
02B0 0100
02B0 2000
02B0 2400
02B0 4000
02B0 4080
02B4 0000
02B4 0800
02B8 0000
02B8 0100
02BA 0000
02BA 0100
02BC 0000
02C0 0000
02C0 0400
02C4 0000
02C4 0100
02C8 0000
02C8 0800
02C8 1000
02C8 1100
02C8 1800
02C8 1900
02C8 2000
02C8 4000
02D0 0000
0295 FFFF
0296 003F
0296 FFFF
029A 01FF
029B FFFF
029C 01FF
029C 02FF
02A0 7FFF
02A1 FFFF
02A2 7FFF
02A2 FFFF
02A3 7FFF
02A3 FFFF
02A4 7FFF
02A4 FFFF
02A7 FFFF
02A8 00FF
02AB FFFF
02AC 0FFF
02AC 3FFF
02AC 40FF
02AC FFFF
02AD 7FFF
02AD FFFF
02AE 7FFF
02AF FFFF
02B0 00FF
02B0 1FFF
02B0 23FF
02B0 3FFF
02B0 407F
02B3 FFFF
02B4 07FF
02B7 FFFF
02B8 00FF
02B8 FFFF
02BA 00FF
02BB FFFF
02BF FFFF
02C0 03FF
02C3 FFFF
02C4 00FF
02C7 FFFF
02C8 07FF
02C8 0FFF
02C8 10FF
02C8 17FF
02C8 18FF
02C8 FFFF
02C8 3FFF
02CF FFFF
02D2 0FFF
64K - 64
64
Reserved
Timer5
Reserved
256K - 64
512
PLL Controller 1 (Main)
Reserved
128K - 512
512
Reserved
256K - 512
32K
Reserved
EDMA3 Channel Controller (TPCC)
Reserved
96K
32K
EDMA3 Transfer Controller 0 (TPTC0)
EDMA3 Transfer Controller 1 (TPTC1)
EDMA3 Transfer Controller 2 (TPTC2)
EDMA3 Transfer Controller 3 (TPTC3)
EDMA3 Transfer Controller 4 (TPTC4)
EDMA3 Transfer Controller 5 (TPTC5)
Reserved
32K
32K
32K
32K
32K
192K
256
Reserved
256K - 256
4K
Reserved
Power/Sleep Controller (PSC)
Reserved
12K
256
Reserved
48K - 256
32K
Reserved
Embedded Trace Buffer 0 (ETB0)
Embedded Trace Buffer 1 (ETB1)
Embedded Trace Buffer 2 (ETB2)
Reserved
32K
32K
96K
256
GPIO
8K - 256
1K
Reserved
Reserved
7K
Reserved
128
I2C Data and Control
Reserved
256K - 128
2K
Semaphore
254K
256
Reserved
VCP2 Control
128K - 256
256
Reserved
TCP2 Control
128K - 256
256K
1K
Reserved
Antenna Interface Control
Reserved
255K
256
Reserved
SMGII Control
256K - 256
2K
Reserved
EMAC Control
2K
Reserved
256
EMAC Interrupt Controller
Reserved
2K - 256
256
MDIO
2K - 256
8K
Reserved
EMAC Descriptor Memory
Reserved
496K
132K
RapidIO
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