TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the SPRS358E device-specific
data manual to make it an SPRS358F revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320TCI6487/8
device, have been incorporated.
TCI6487/8 Revision History
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 8.7
PLL1 and PLL1 Controller:
Modified Figure 8-10, PLL Controller Diagram
Section 8.7.4 PLL1 Controller Input and Output Electrical Data/Timing:
Modified Timing No. 1 (AIF Used, CORECLKSEL=1) MAX Value to 16.276 ns in Table 8-31, Timing
Requirements for SYSCLK and ALTCORECLK
Section 8.12.2 EMAC Peripheral Register Descriptions:
Modified Table 8-48 title to EMAC Interrupt Control (EMIC) Registers
Submit Documentation Feedback
Revision History
7
TI [ TEXAS INSTRUMENTS ]
