TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.5.2 System Event Routing
Additional system events are routed to each of the C64x+ Megamodules to provide chip-level events that
are not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events.
Additionally, error-class events or infrequently used events are also routed through the system event
router to offload the C64x+ Megamodule interrupt selector. This is accomplished through Chip Interrupt
Controllers, CIC[2:0], with one controller per C64x+ Megamodule. This is clocked using CPU/6.
The event controllers consist of simple combination logic to provide sixteen events to each C64x+
Megamodule, plus the TPCC.
These events are routed to the C64x+ Megamodules for AET purposes, from those TPCC and FSYNC
events that are not otherwise provided to each C64x+ Megamodule. The event controllers each include
two event combiners to provide two combined events to each C64x+ Megamodule, for use. Each of the 16
event outputs from the controllers can select any of the 64 inputs, or either of the two combined events to
pass on to their respective C64x+ Megamodule.
Table 8-12 lists the system events that are available to each C64x+ Megamodule through their respective
event controllers. Note that n implies the event number matches the C64x+ Megamodule number to which
it is routed.
Table 8-12. C64x+ Megamodule Chip Interrupt Controller Event List CIC[2:0]
EVENT CHANNEL
EVENT
EVT0
EVENT DESCRIPTION
Output of Event Controller 0 for Events [31:2]
0
1
EVT1
Output of Event Controller 1 for Events [63:32]
Reserved
2
Unused
Unused
I2CINT
3
Reserved
4
Error Interrupt
5
FSERR1
RIOINT7
FSERR2
VCPINT
TCPINT
RINT0
Error/Alarm Interrupt 1
Error Interrupt
6
7
Error/Alarm Interrupt 2
Error Interrupt
8
9
Error Interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
McBSP0 Receive Interrupt
McBSP0 Transmit Interrupt
McBSP1 Receive Interrupt
McBSP1 Transmit Interrupt
McBSP0 Receive EDMA Event
McBSP0 Transmit EDMA Event
McBSP1 Receive EDMA Event
McBSP1 Transmit EDMA Event
I2C Receive EDMA Event
I2C Transmit EDMA Event
FSYNC Event 18
XINT0
RINT1
XINT1
REVT0
XEVT0
REVT1
XEVT1
IREVT
IXEVT
FSEVT18
FSEVT19
FSEVT20
FSEVT21
FSEVT22
FSEVT23
FSEVT24
FSEVT25
FSEVT26
FSEVT27
FSYNC Event 19
FSYNC Event 20
FSYNC Event 21
FSYNC Event 22
FSYNC Event 23
FSYNC Event 24
FSYNC Event 25
FSYNC Event 26
FSYNC Event 27
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