TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
Table 8-11. Interrupts (continued)
EVENT CHANNEL
EVENT
FSEVT15
FSEVT16
FSEVT17
TINT0L
EVENT DESCRIPTION
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
53
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Frame Synchronization Event 15
Frame Synchronization Event 16
Frame Synchronization Event 17
Timer 0 Interrupt Low
Timer 0 Interrupt High
Timer 1 Interrupt Low
Timer 1 Interrupt High
Timer 2 Interrupt Low
Timer 2 Interrupt High
Timer 3 Interrupt Low
Timer 3 Interrupt High
Timer 4 Interrupt Low
Timer 4 Interrupt High
Timer 5 Interrupt Low
Timer 5 Interrupt High
GPIO Interrupt 0
TINT0H
TINT1L
TINT1H
TINT2L
TINT2H
TINT3L
TINT3H
TINT4L
TINT4H
TINT5L
TINT5H
GPINT0
GPINT1
GPIO Interrupt 1
GPINT2
GPIO Interrupt 2
GPINT3
GPIO Interrupt 3
GPINT4
GPIO Interrupt 4
GPINT5
GPIO Interrupt 5
GPINT6
GPIO Interrupt 6
GPINT7
GPIO Interrupt 7
GPINT8
GPIO Interrupt 8
GPINT9
GPIO Interrupt 9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
TPCC_GINT
TPCC_INT0
TPCC_INT1
TPCC_INT2
TPCC_INT3
TPCC_INT4
TPCC_INT5
TPCC_INT6
TPCC_INT7
Unused
GPIO Interrupt 10
GPIO Interrupt 11
GPIO Interrupt 12
GPIO Interrupt 13
GPIO Interrupt 14
GPIO Interrupt 15
EDMA Channel Global Completion Interrupt
TPCC Completion Interrupt - Mask 0
TPCC Completion Interrupt - Mask 1
TPCC Completion Interrupt - Mask 2
TPCC Completion Interrupt - Mask 3
TPCC Completion Interrupt - Mask 4
TPCC Completion Interrupt - Mask 5
TPCC Completion Interrupt - Mask 6
TPCC Completion Interrupt - Mask 7
Reserved
RIOINT (2n)(4)
RIOINT (2n+1)(4)
AIF_EVT0
RapidIO Interrupt (2n)
RapidIO Interrupt (2n+1)
Error/Alarm Event 0
(4) RIOINT interrupts are received by the C64x+ Megamodules, as follows:
•
•
•
C64x+ Megamodule Core 0 receives RIOINT[1:0]
C64x+ Megamodule Core 1 receives RIOINT[3:2]
C64x+ Megamodule Core 2 receives RIOINT[5:0]
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