TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
Table 8-13. TPCC Interrupt Controller Event List (CIC3) (continued)
EVENT CHANNEL
EVENT
TINT5L
EVENT DESCRIPTION
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Timer Interrupt Low
Timer Interrupt High
AIF Capture Buffer Event
Frame Synchronization Event 29
Debug Event
TINT5H
AIF_BUFEVT
FSEVT29
RAC_DEVENT0
RAC_DEVENT1
GPINT0
Debug Event
GPIO Event
GPINT1
GPIO Event
GPINT2
GPIO Event
GPINT3
GPIO Event
GPINT4
GPIO Event
CIC0_EVT14
CIC0_EVT15
CIC1_EVT14
CIC1_EVT15
CIC2_EVT14
CIC2_EVT15
CIC_EVT_o[14] from Chip Interrupt Controller[0]
CIC_EVT_o[15] from Chip Interrupt Controller[0]
CIC_EVT_o[14] from Chip Interrupt Controller[1]
CIC_EVT_o[15] from Chip Interrupt Controller[1]
CIC_EVT_o[14] from Chip Interrupt Controller[2]
CIC_EVT_o[15] from Chip Interrupt Controller[2]
8.5.3 External Interrupts Electrical Data/Timing
Table 8-14. Timing Requirements for External Interrupts(1)
(see Figure 8-5)
NO.
PARAMETERS
Width of the NMI interrupt pulse low
Width of the NMI interrupt pulse high
MIN
6P
MAX UNIT
1
2
tw(NMIL)
tw(NMIH)
ns
ns
6P
(1) P = 1/CPU clock frequency, in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2
1
NMI
Figure 8-5. NMI Interrupt Timing
108
Peripheral Information and Electrical Specifications
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