TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Table 5-33. HPI8 Mode Switching Characteristics
5416-120
5416-160
PARAMETER
Enable time, HD driven from DS low
UNIT
MIN
MAX
ten(DSL-HD)
0
10
ns
Case 1a: Memory accesses when DMAC is active
36P + 10 –
tw(DSH)
in 32-bit mode and tw(DSH) < 36P(1)
Case 1b: Memory accesses when DMAC is active
10
in 32-bit mode and tw(DSH)≥ 36P(1)
Case 1c: Memory accesses when DMAC is active
in 16-bit mode and tw(DSH) < I8P(1)
18P + 10 –
tw(DSH)
Delay time, DS low to HD valid
for first byte of an HPI read
td(DSL-HDV1)
Case 1d: Memory accesses when DMAC is active
ns
10
in 16-bit mode and tw(DSH)≥ I8P(1)
Case 2a: Memory accesses when DMAC is inactive
and tw(DSH) < 10P(1)
10P + 10 –
tw(DSH)
Case 2b: Memory accesses when DMAC is inactive
10
and tw(DSH)≥ 10P(1)
Case 3: Register accesses
10
10
td(DSL-HDV2)
th(DSH-HDV)R
tv(HYH-HDV)
td(DSH-HYL)
Delay time, DS low to HD valid for second byte of an HPI read
Hold time, HD valid after DS high, for a HPI read
Valid time, HD valid after HRDY high
ns
ns
ns
ns
0
2
8
Delay time, DS high to HRDY low(2)
Case 1a: Memory accesses when DMAC is active
18P + 6
36P + 6
10P + 6
in 16-bit mode(1)
Case 1b: Memory accesses when DMAC is active
in 32-bit mode(1)
Delay time, DS high to HRDY
high(2)
td(DSH-HYH)
ns
Case 2: Memory accesses when DMAC is inac-
tive(1)
Case 3: Write accesses to HPIC register(3)
6P + 6
td(HCS-HRDY)
td(COH-HYH)
td(COH-HTX)
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
6
9
6
ns
ns
ns
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output
td(COH-GPIO)
5
ns
(1) DMAS stands for direct memory access controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
(2) The HRDY output is always high when the HCS input is high, regardless of DS timings.
(3) This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
Electrical Specifications
87
TI [ TEXAS INSTRUMENTS ]
