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TMS320VC5416ZGU160 参数 Datasheet PDF下载

TMS320VC5416ZGU160图片预览
型号: TMS320VC5416ZGU160
PDF下载: 下载PDF文件 查看货源
内容描述: TMS320VC5416定点数字信号处理器 [TMS320VC5416 Fixed-Point Digital Signal Processor]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 98 页 / 855 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320VC5416  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS095OMARCH 1999REVISED JANUARY 2005  
(1)  
Table 5-30. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)  
5416-120  
5416-160  
UNIT  
MASTER  
SLAVE  
MIN  
MIN MAX  
MAX  
tsu(BDRV-BCKXL)  
th(BCKXL–BDRV)  
Setup time, BDR valid before BCLKX low  
Hold time, BDR valid after BCLKX low  
12  
4
2 – 6P(2)  
5 + 12P(2)  
ns  
ns  
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
(2) P = 0.5 * processor clock.  
(1)  
Table 5-31. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)  
5416-120  
5416-160  
PARAMETER  
UNIT  
MASTER(2)  
SLAVE  
MIN  
MIN  
MAX  
MAX  
th(BCKXH-BFXL)  
td(BFXL-BCKXL)  
td(BCKXH-BDXV)  
Hold time, BFSX low after BCLKX high(3)  
Delay time, BFSX low to BCLKX low(4)  
Delay time, BCLKX high to BDX valid  
D – 3 D + 4  
T – 4 T + 3  
ns  
ns  
ns  
– 4  
5
6P + 2(5)  
6P – 4(5)  
4P + 2(5)  
10P + 17(5)  
10P + 17(5)  
8P + 17(5)  
Disable time, BDX high impedance following last data bit from  
BCLKX high  
tdis(BCKXH-BDXHZ)  
td(BFXL-BDXV)  
– 2  
4
ns  
ns  
Delay time, BFSX low to BDX valid  
C – 2 C + 4  
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.  
(2) T = BCLKX period = (1 + CLKGDV) * 2P  
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even  
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and (CLKGDV/2 + 1) * 2P when CLKGDV is even  
(3) FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input  
on BFSX and BFSR is inverted before being used internally.  
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP  
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP  
(4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the  
master clock (BCLKX).  
(5) P = 0.5 * processor clock.  
MSB  
LSB  
BCLKX  
t
t
h(BCKXH-BFXL)  
d(BFXL-BCKXL)  
BFSX  
t
t
t
t
dis(BCKXH-BDXHZ)  
d(BCKXH-BDXV)  
(n-2)  
d(BFXL-BDXV)  
BDX  
Bit 0  
Bit(n-1)  
Bit(n-1)  
(n-3)  
(n-4)  
su(BDRV-BCKXL)  
t
h(BCKXL-BDRV)  
(n-2)  
BDR  
Bit 0  
(n-3)  
(n-4)  
Figure 5-27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1  
Electrical Specifications  
85