TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.11.2 HPI16 Mode
Table 5-34 and Table 5-35 assume testing over recommended operating conditions and P = 0.5 *
processor clock (see Figure 5-32 through Figure 5-34). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These
timings are shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP
Reference Set,Volume 5: Enhanced Peripherals (literature number SPRU302) for additional information.
Table 5-34. HPI16 Mode Timing Requirements
5416-120
5416-160
UNIT
MIN MAX
tsu(HBV-DSL)
th(DSL-HBV)
tsu(HAV-DSH)
tsu(HAV-DSL)
th(DSH-HAV)
tw(DSL)
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
6
5
5
ns
ns
ns
ns
ns
ns
ns
–(4P– 6)(1)
1
30
tw(DSH)
Pulse duration, DS high
10
Reads 10P + 30(1)
Writes 10P + 10(1)
Reads 16P + 30(1)
Writes 16P + 10(1)
Reads 24P + 30(1)
Writes 24P + 10(1)
8
Memory accesses with no DMA activity.
Cycle time, DS rising edge to
next DS rising edge
Memory accesses with 16-bit DMA activ-
ity.
tc(DSH-DSH)
ns
Memory accesses with 32-bit DMA activ-
ity.
tsu(HDV-DSH)W
th(DSH-HDV)W
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
ns
ns
2
(1) P = 0.5 * processor clock.
90
Electrical Specifications
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