TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Second Byte
First Byte
Second Byte
HAS
t
su(HBV-DSL)
t
su(HSL-DSL)
t
h(DSL-HBV)
HAD
(see Note A)
Valid
Valid
‡
su(HBV-DSL)
t
t
h(DSL-HBV)
(see Note B)
HBIL
HCS
t
w(DSH)
t
w(DSL)
HDS
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
t
d(DSL-HDV1)
t
h(DSH-HDV)R
HD READ
Valid
Valid
Valid
t
su(HDV-DSH)
v(HYH-HDV)
t
h(DSH-HDV)W
HD WRITE
Valid
Valid
Valid
t
d(COH-HYH)
Processor
CLK
A. HAD refers to HCNTL0, HCNTL1, and HR/W.
B. When HAS is not used (HAS always high)
Figure 5-28. Using HDS to Control Accesses (HCS Always Low)
88
Electrical Specifications