TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Table 5-26. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1)
5416-120
5416-160
UNIT
MASTER
SLAVE
MIN MAX
MIN MAX
tsu(BDRV-BCKXL)
th(BCKXH-BDRV)
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX high
12
4
2 – 6P(2)
5 + 12P(2)
ns
ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 0.5 * processor clock.
Table 5-27. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1)
5416-120
5416-160
PARAMETER
UNIT
MASTER(2)
MIN MAX
SLAVE
MIN
MAX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
td(BCKXL-BDXV)
Hold time, BFSX low after BCLKX low(3)
Delay time, BFSX low to BCLKX high(4)
Delay time, BCLKX low to BDX valid
C –3 C + 4
T – 4 T + 3
ns
ns
ns
– 4
5
6P + 2(5) 10P + 17(5)
6P – 4(5) 10P + 17(5)
Disable time, BDX high impedance following last data bit from
BCLKX low
tdis(BCKXL-BDXHZ)
td(BFXL-BDXV)
– 2
4
ns
ns
D –
2
Delay time, BFSX low to BDX valid
D + 4 4P + 2(5)
8P + 17(5)
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) *2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and (CLKGDV/2 + 1) * 2P when CLKGDV is even
(3) FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
(4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the
master clock (BCLKX).
(5) P = 0.5 * processor clock.
MSB
LSB
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXH-BDRV)
(n-2)
BDR
Bit 0
(n-3)
(n-4)
Figure 5-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Electrical Specifications
83
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