TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Table 5-35. HPI16 Mode Switching Characteristics
5416-120
5416-160
PARAMETER
Delay time, DS low to HD driven
UNIT
MIN
MAX
td(DSL-HDD)
0
10
Case 1a: Memory accesses initiated immediately following a write
when DMAC is active in 32-bit mode and tw(DSH) was < 26P
48P + 20 – tw(DSH)
24P + 20
Case 1b: Memory access not immediately following a write when
DMAC is active in 32-bit mode
Case 1c: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and tw(DSH) was < 18P
Delay time, DS
low to HD valid
for first word of
an HPI read
32P + 20 – tw(DSH)
16P + 20
ns
td(DSL-HDV1)
Case 1d: Memory accesses not immediately following a write when
DMAC is active in 16-bit mode
Case 2a: Memory accesses initiated immediately following a write
when DMAC is inactive and tw(DSH) was < 10P
20P + 20 – tw(DSH)
10P + 20
Case 2b: Memory accesses not immediately following a write when
DMAC is inactive
Memory writes when no DMA is active
10P + 5
16P + 5
24P + 5
Delay time, DS
td(DSH-HYH)
high to HRDY Memory writes with one or more 16-bit DMA channels active
ns
high
Memory writes with one or more 32-bit DMA channels active
tv(HYH-HDV)
th(DSH-HDV)R
td(COH-HYH)
td(DSL-HYL)
td(DSH-HYL)
Valid time, HD valid after HRDY high
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
Delay time, DS low to HRDY low
7
ns
ns
ns
ns
ns
1
6
5
12
12
Delay time, DS high to HRDY low
HCS
t
w(DSH)
t
c(DSH−DSH)
HDS
t
t
su(HBV−DSL)
w(DSL)
t
su(HBV−DSL)
t
t
h(DSL−HBV)
h(DSL−HBV)
HR/W
t
su(HAV−DSL)
t
h(DSH−HAV)
HA[17:0]
Valid Address
Valid Address
t
h(DSH−HDV)R
t
d(DSL−HDV1)
t
t
h(DSH−HDV)R
d(DSL−HDV1)
Data
HD[15:0]
HRDY
Data
t
d(DSL−HDD)
t
d(DSL−HDD)
t
v(HYH−HDV)
t
v(HYH−HDV)
t
t
d(DSL−HYL)
d(DSL−HYL)
Figure 5-32. Nonmultiplexed Read Timings
Electrical Specifications
91
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