TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.11 Host-Port Interface Timing
5.5.11.1 HPI8 Mode
Table 5-32 and Table 5-33 assume testing over recommended operating conditions and P = 0.5 *
processor clock (see Figure 5-28 through Figure 5-31). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands
for HCNTL0, HCNTL1, and HR/W.
Table 5-32. HPI8 Mode Timing Requirements
5416-120
5416-160
UNIT
MIN
MAX
Setup time, HBIL and HAD valid before DS low (when HAS is not used), or HBIL and HAD
valid before HAS low
tsu(DSL-HBV)
th(DSL-HBV)
6
ns
ns
Hold time, HBIL and HAD valid after DS low (when HAS is not used), or HBIL and HAD
valid after HAS low
3
tsu(HSL-DSL)
tw(DSL)
Setup time, HAS low before DS low
Pulse duration, DS low
8
13
7
ns
ns
ns
ns
ns
tw(DSH)
Pulse duration, DS high
tsu(HDV-DSH)
th(DSH-HDV)W
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
3
2
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose
input
tsu(GPIO-COH)
th(GPIO-COH)
3
0
ns
ns
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
86
Electrical Specifications
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