TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Table 3-16. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DRR20
DESCRIPTION
DEC
HEX
20
32
33
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
DRR10
DXR20
DXR10
TIM
21
34
22
35
23
36
24
PRD
37
25
Timer Period Register
TCR
38
26
Timer Control Register
—
39
27
Reserved
SWWSR
BSCR
—
40
28
Software Wait-State Register
Bank-Switching Control Register
Reserved
41
29
42
2A
SWCR
HPIC
43
2B
Software Wait-State Control Register
HPI Control Register (HMODE = 0 only)
Reserved
44
2C
2D-2F
30
—
45-47
48
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
McBSP 2 Subbank Address Register(1)
McBSP 2 Subbank Data Register(1)
Reserved
McBSP 0 Subbank Address Register(1)
McBSP 0 Subbank Data Register(1)
Reserved
49
31
50
32
51
33
52
34
53
35
54-55
56
36-37
38
SPSA0
SPSD0
—
57
39
58-59
60
3A-3B
3C
3D
3E
GPIOCR
GPIOSR
CSIDR
—
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
61
62
63
3F
Reserved
DRR21
DRR11
DXR21
DXR11
—
64
40
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
McBSP 1 Subbank Address Register(1)
McBSP 1 Subbank Data Register(1)
Reserved
65
41
66
42
67
43
68-71
72
44-47
48
SPSA1
SPSD1
—
73
49
74-83
84
4A-53
54
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
DMA Priority and Enable Control Register
DMA Subbank Address Register(2)
DMA Subbank Data Register with Autoincrement(2)
DMA Subbank Data Register(2)
Clock Mode Register (CLKMD)
Reserved
85
55
86
56
87
57
88
58
89-95
59-5F
(1) See Table 3-17 for a detailed description of the McBSP control registers and their subaddresses.
(2) See Table 3-18 for a detailed description of the DMA subbank addressed registers.
46
Functional Overview
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