TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
3.18 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-19.
Table 3-19. Interrupt Locations and Priorities
TRAP/INTR
NUMBER (K)
NAME
LOCATION DECIMAL HEX
PRIORITY
FUNCTION
RS, SINTR
0
1
0
4
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78-7F
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
NMI, SINT16
SINT17
2
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Software interrupt #17
SINT18
3
12
Software interrupt #18
SINT19
4
16
Software interrupt #19
SINT20
5
20
Software interrupt #20
SINT21
6
24
Software interrupt #21
SINT22
7
28
Software interrupt #22
SINT23
8
32
Software interrupt #23
SINT24
9
36
Software interrupt #24
SINT25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30-31
40
Software interrupt #25
SINT26
44
Software interrupt #26
SINT27
48
Software interrupt #27
SINT28
52
Software interrupt #28
SINT29
56
Software interrupt #29
SINT30
60
Software interrupt #30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT, SINT3
RINT0, SINT4
XINT0, SINT5
RINT2, SINT6
XINT2, SINT7
INT3, SINT8
HINT, SINT9
RINT1, SINT10
XINT1, SINT11
DMAC4,SINT12
DMAC5,SINT13
Reserved
64
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer interrupt
68
4
72
5
76
6
80
7
McBSP #0 receive interrupt (default)
McBSP #0 transmit interrupt (default)
McBSP #2 receive interrupt (default)
McBSP #2 transmit interrupt (default)
External user interrupt #3
HPI interrupt
84
8
88
9
92
10
11
12
13
14
15
16
—
96
100
104
108
112
116
120-127
McBSP #1 receive interrupt (default)
McBSP #1 transmit interrupt (default)
DMA channel 4 (default)
DMA channel 5 (default)
Reserved
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in
Figure 3-23.
15
14
13
12
11
10
9
8
Reserved
DMAC5
DMAC4
XINT1
RINT1
HINT
INT3
7
6
5
4
3
2
1
0
XINT2
RINT2
XINT0
RINT0
TINT
INT2
INT1
INT0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3-23. IFR and IMR Registers
50
Functional Overview
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