TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
Table 3-12. DMA Synchronization Events (continued)
DSYN VALUE
0101b
DMA SYNCHRONIZATION EVENT
McBSP1 receive event
0110b
McBSP1 transmit event
0111b
McBSP0 receive event - ABIS mode
McBSP0 transmit event - ABIS mode
McBSP2 receive event - ABIS mode
McBSP2 transmit event - ABIS mode
McBSP1 receive event - ABIS mode
McBSP1 transmit event - ABIS mode
Timer interrupt event
1000b
1001b
1010b
1011b
1100b
1101b
1110b
INT3 goes active
1111b
Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on
the number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt
sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the
McBSP. When the device is reset, the interrupts from these three DMA channels are deselected. The
INTSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 3-13.
Table 3-13. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
IMR/IFR[10]
BRINT1
IMR/IFR[11]
BXINT1
BXINT2
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
3.13 General-Purpose I/O Pins
In addition to the standard BIO and XF pins, the device has pins that can be configured for
general-purpose I/O. These pins are:
•
18 McBSP pins
–
–
–
–
–
–
BCLKX0/1/2,
BCLKR0/1/2
BDR0/1/2
BFSX0/1/2
BFSR0/1/2
BDX0/1/2
•
8 HPI data pins
HD0-HD7
–
The general-purpose I/O function of these pins is only available when the primary pin function is not
required.
3.13.1 McBSP Pins as General-Purpose I/O
When the receive or transmit portion of a McBSP is in reset, its pins can be configured as
general-purpose inputs or outputs. For more details on this feature, see Section 3.8.
Functional Overview
43
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