TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
3.16 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register
within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected
register. Table 3-17 shows the McBSP control registers and their corresponding subaddresses.
Table 3-17. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
SUB- AD-
DRESS
DESCRIPTION
NAME
ADDRESS
39h
NAME
ADDRESS
49h
NAME
ADDRESS
35h
SPCR10
SPCR20
RCR10
SPCR11
SPCR21
RCR11
SPCR12
SPCR22
RCR12
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 1
39h
49h
35h
Serial port control register 2
39h
49h
35h
Receive control register 1
RCR20
39h
RCR21
49h
RCR22
35h
Receive control register 2
XCR10
39h
XCR11
49h
XCR12
35h
Transmit control register 1
XCR20
39h
XCR21
49h
XCR22
35h
Transmit control register 2
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
39h
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
SRGR12
SRGR22
MCR12
MCR22
RCERA2
RCERA2
XCERA2
XCERA2
PCR2
35h
Sample rate generator register 1
Sample rate generator register 2
Multichannel control register 1
Multichannel control register 2
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
Additional channel enable register for
128-channel selection
RCERC0
RCERD0
XCERC0
XCERD0
RCERE0
RCERF0
XCERE0
XCERF0
RCERG0
RCERH0
XCERG0
XCERH0
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
RCERC1
RCERD1
XCERC1
XCERD1
RCERE1
RCERF1
XCERE1
XCERF1
RCERG1
RCERH1
XCERG1
XCERH1
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
RCERC2
RCERD2
XCERC2
XCERD2
RCERE2
RCERF2
XCERE2
XCERF2
RCERG2
RCERH2
XCERG2
XCERH2
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Functional Overview
47
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