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TMS320VC5416ZGU160 参数 Datasheet PDF下载

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型号: TMS320VC5416ZGU160
PDF下载: 下载PDF文件 查看货源
内容描述: TMS320VC5416定点数字信号处理器 [TMS320VC5416 Fixed-Point Digital Signal Processor]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 98 页 / 855 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320VC5416  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS095OMARCH 1999REVISED JANUARY 2005  
3.12.8 DMA Transfer in Doubleword Mode  
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two  
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically  
updated following each transfer. In this mode, each 32-bit word is considered to be one element.  
3.12.9 DMA Channel Index Registers  
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA  
transfer mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame  
index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not  
the element transfer is the last in the current frame. The normal adjustment value (element index) is  
contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for  
the end of the frame, is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.  
The element index and the frame index affect address adjustment as follows:  
Element index: For all except the last transfer in the frame, the element index determines the amount  
to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as  
selected by the SIND/DIND bits.  
Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as  
selected by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers.  
3.12.10 DMA Interrupts  
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is  
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The  
available modes are shown in Table 3-11.  
Table 3-11. DMA Interrupts  
MODE  
ABU (non-decrement)  
ABU (non-decrement)  
Multiframe  
DINM  
IMOD  
INTERRUPT  
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only  
At half buffer and full buffer  
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)  
At end of frame and end of block (DMCTRn = 0)  
No interrupt generated  
Multiframe  
Either  
Either  
No interrupt generated  
3.12.11 DMA Controller Synchronization Events  
The transfers associated with each DMA channel can be synchronized to one of several events. The  
DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of  
possible events and the DSYN values are shown in Table 3-12.  
Table 3-12. DMA Synchronization Events  
DSYN VALUE  
0000b  
DMA SYNCHRONIZATION EVENT  
No synchronization used  
0001b  
McBSP0 receive event  
McBSP0 transmit event  
McBSP2 receive event  
McBSP2 transmit event  
0010b  
0011b  
0100b  
42  
Functional Overview