TMS320VC5416
Fixed-Point Digital Signal Processor
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SPRS095O–MARCH 1999–REVISED JANUARY 2005
3.13.2 HPI Data Pins as General-Purpose I/O
The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when
the HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two
memory-mapped registers are used to control the GPIO function of the HPI data pins—the gen-
eral-purpose I/O control register (GPIOCR) and the general-purpose I/O status register (GPIOSR). The
GPIOCR is shown in Figure 3-20.
15
8
Reserved
0
7
6
5
4
3
2
1
0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3-20. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
The direction bits (DIRx) are used to configure HD0-HD7 as inputs or outputs.
The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in
Figure 3-21.
15
8
Reserved
0
7
6
5
4
3
2
1
0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3-21. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
3.14 Device ID Register
A read-only memory-mapped register has been added to the device to allow user application software to
identify on which device the program is being executed.
15
8
CHIP ID
R
7
4
3
0
CHIP REVISION
R
SUBSYSID
R
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3-22. Device ID Register (CSIDR) [MMR Address 003Eh]
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Functional Overview
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