TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Data Space (0000 - 005F)
Hex
Data Space
I/O Space
Hex
0000
0000
0000
Reserved
001F
Data Space
(See Breakout)
0020
0021
0022
DRR20
DRR10
DXR20
005F
0060
0023
0024
002F
0030
0031
0032
0033
DXR10
Scratch-Pad
RAM
Reserved
DRR22
DRR12
DXR22
DXR12
007F
0080
On-Chip
DARAM0
8K Words
1FFF
2000
On-Chip
DARAM1
8K Words
0034
0035
0036
0037
Reserved
RCERA2
XCERA2
3FFF
4000
On-Chip
DARAM2
8K Words
0038
0039
Reserved
Reserved
5FFF
6000
003A
003B
RECRA0
XECRA0
On-Chip
DARAM3
8K Words
003C
003F
0040
0041
Reserved
DRR21
DRR11
DXR21
DXR11
7FFF
8000
On-Chip
DARAM4
8K Words
0042
0043
9FFF
A000
On-Chip
DARAM5
8K Words
0044
0049
004A
Reserved
RCERA1
BFFF
C000
On-Chip
DARAM6
8K Words
004B
XCERA1
004C
005F
Reserved
DFFF
E000
On-Chip
DARAM7
8K Words
FFFF
FFFF
Figure 3-18. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4 DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management
schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed
separately and can be post-incremented, post-decremented, or post-incremented with a specified index
offset.
40
Functional Overview
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