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TMS320VC5416ZGU160 参数 Datasheet PDF下载

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型号: TMS320VC5416ZGU160
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内容描述: TMS320VC5416定点数字信号处理器 [TMS320VC5416 Fixed-Point Digital Signal Processor]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 98 页 / 855 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320VC5416  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS095OMARCH 1999REVISED JANUARY 2005  
3.12.6 DMA in Autoinitialization Mode  
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA  
registers can be preloaded for the next block transfer through the DMA reload registers (DMGSA,  
DMGDA, DMGCR, and DMGFR). Autoinitialization allows:  
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the  
completion of the current block transfers, but with the reload registers, it can reinitialize these values  
for the next block transfer any time after the current block transfer begins.  
Repetitive operation:The CPU does not preload the reload register with new values for each block  
transfer but only loads them on the first block transfer.  
The DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now has its  
own DMA reload register set. For example, the DMA reload register set for channel 0 has DMGSA0,  
DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1, and  
DMGFR1, etc.  
To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown  
in Figure 3-19.  
15  
14  
13  
8
0
FREE  
AUTOIX  
DPRC[5:0]  
DE[5:0]  
7
6
5
IOSEL  
LEGEND: R = Read, W = Write, n = value present after reset  
Figure 3-19. DMPREC Register  
Table 3-10. DMA Reload Register Selection  
AUTOIX  
0 (default)  
1
DMA RELOAD REGISTER USAGE IN AUTO INIT MODE  
All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0  
Each DMA channel uses its own set of reload registers  
3.12.7 DMA Transfer Counting  
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit  
fields that represent the number of frames and the number of elements per frame to be transferred.  
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum  
number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented  
upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit  
counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1.  
A frame count of 0 (default value) means the block transfer contains a single frame.  
Element count. This 16-bit value defines the number of elements per frame. This counter is  
decremented after the read transfer of each element. The maximum number of elements per frame is  
65536 (DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter  
is reloaded with the DMA global count reload register (DMGCR).  
Functional Overview  
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