ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE
ECLKOUT
CEx
1
2
4
4
4
9
2
4
5
5
5
9
3
BE[3:0]
BE1
Bank
BE2
BE3
BE4
EA[21:13]
Column
EA[11:2]
EA12
10
ED[31:0]
D1
D2
D3
D4
†
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
8
8
†
11
11
†
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 23. SDRAM Write Command
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443