ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
SYNCHRONOUS DRAM TIMING
†
timing requirements for synchronous DRAM cycles (see Figure 22)
C6211−150
C6211−167
C6211B−150
C6211B−167
C6211BGFNA−150
NO.
UNIT
MIN MAX
MIN
MAX
MIN MAX
Setup time, read EDx valid before
ECLKOUT high
6
7
t
t
2.5
1
2.5
2.5
ns
ns
su(EDV-EKOH)
Hold time, read EDx valid after
ECLKOUT high
2.5
2
h(EKOH-EDV)
†
The C6211/C6211B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous DRAM
†‡
cycles (see Figure 22−Figure 28)
C6211−150
C6211−167
C6211B−150
C6211B−167
C6211BGFNA−150
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Delay time, ECLKOUT high to CEx
valid
1
2
t
t
t
t
t
t
t
t
t
t
1.5
6.5
6.5
1
6.5
1.2
6.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKOH-CEV)
d(EKOH-BEV)
d(EKOH-BEIV)
d(EKOH-EAV)
d(EKOH-EAIV)
d(EKOH-CASV)
d(EKOH-EDV)
d(EKOH-EDIV)
d(EKOH-WEV)
d(EKOH-RAS)
Delay time, ECLKOUT high to BEx
valid
6.5
6.5
6.5
6.5
Delay time, ECLKOUT high to BEx
invalid
3
1.5
1
1.2
Delay time, ECLKOUT high to EAx
valid
4
6.5
Delay time, ECLKOUT high to EAx
invalid
5
1.5
1.5
1
1
1.2
1.2
Delay time, ECLKOUT high to
ARE/SDCAS/SSADS valid
8
6.5
7
6.5
7
6.5
7
Delay time, ECLKOUT high to EDx
valid
9
Delay time, ECLKOUT high to EDx
invalid
10
11
12
1.5
1.5
1.5
1
1
1
1.2
1.2
1.2
Delay time, ECLKOUT high to
AWE/SDWE/SSWE valid
6.5
6.5
6.5
6.5
6.5
6.5
Delay time, ECLKOUT high to
AOE/SDRAS/SSOE valid
†
‡
The C6211/C6211B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
54
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