ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
ECLKOUT
CEx
1
1
2
3
BE[3:0]
BE1
BE2
BE3
BE4
4
5
5
5
Bank
EA[21:13]
EA[11:2]
4
Column
4
EA12
6
7
D2
ED[31:0]
D1
D3
D4
†
AOE/SDRAS/SSOE
8
8
†
†
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 22. SDRAM Read Command (CAS Latency 3)
55
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