ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC
ECLKOUT
1
1
CEx
BE[3:0]
4
5
EA[21:13]
EA[11:2]
Bank
4
5
EA12
ED[31:0]
12
11
12
11
†
†
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
†
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 26. SDRAM DEAC Command
REFR
ECLKOUT
1
1
CEx
BE[3:0]
EA[21:2]
EA12
ED[31:0]
12
8
12
8
†
AOE/SDRAS/SSOE
†
†
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 27. SDRAM REFR Command
58
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TI [ TEXAS INSTRUMENTS ]
