ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT
1
1
CEx
2
3
BE1
BE2
BE3
EA
BE4
7
BE[3:0]
4
5
EA[21:2]
ED[31:0]
6
Q1
Q2
Q3
Q4
8
8
†
ARE/SDCAS/SSADS
9
9
†
†
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 20. SBSRAM Read Timing
ECLKOUT
1
2
1
3
CEx
BE[3:0]
BE1
BE2
Q2
BE3
5
BE4
Q4
4
EA[21:2]
ED[31:0]
EA
10
11
12
Q1
Q3
8
8
†
†
ARE/SDCAS/SSADS
AOE/SDRAS/SSOE
12
†
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 21. SBSRAM Write Timing
53
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TI [ TEXAS INSTRUMENTS ]
