ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Hold = 2
Strobe = 3
Not Ready
ECLKOUT
CEx
8
8
8
8
9
9
9
9
BE[3:0]
BE
EA[21:2]
ED[31:0]
Address
Write Data
†
†
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
10
10
†
AWE/SDWE/SSWE
7
7
6
6
ARDY
†
AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 19. Asynchronous Memory Write Timing
51
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