TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
external memory interface (continued)
B has access to the interface. The external memory interface is also shared with the host port interface (HPI).
The XIO pin is used to select between the external memory interface and the hostport interface. When the XIO
pin is high, the external memory interface is active, and when it is low, the host port interface is active.
processor mode status register (PMST)
Each subsystem has a processor-mode status register (PMST) that controls memory configuration. The bit
layout of the PMST register is shown in Figure 1
15
7
6
5
4
3
2
1
0
IPTR
R/W
MP/MC
R/W
OVLY
R/W
AVIS
R/W
DROM
R/W
CLKOFF
R/W
SMUL
R/W
SST
R/W
LEGEND: R = Read, W = Write
Figure 1. Processor Mode Status Register (PMST) Bit Layout
The functions of the PMST register bits are illustrated in the memory map. The MP/MC bit is used to map the
upper address range of all program space pages (x8000–xFFFF) as either external or internal memory. The
OVLY bit is used to overlay the on-chip DARAM0 and SARAM1 blocks from dataspace onto to program space.
Similarly, the DROM bit is used to overlay the SARAM2 block from program space onto data space. See the
TMS320C54x DSP CPU and Peripherals Reference Set, Volume 1 (literature number SPRU131) for a
description of the other bits of the PMST register.
Due to the dual-processor configuration and the several EMIF/HPI options available, the MP/MC bit is initialized
at the time of device reset to a logic level that is dependent on the XIO, HMODE, and SELA/B pins. Table 1
shows the initialized logic level of the MP/MC bit and how it depends on these pins.
Table 1. MP/MC Bit Logic Levels at Reset
’5420 PINS
MP/MC BIT
XIO
0
HMODE
SELA/B
SUBSYSTEM A
SUBSYSTEM B
X
0
1
1
X
X
0
1
0
1
1
0
0
1
0
1
1
1
1
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