TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
HOST-PORT INTERFACE SIGNALS (CONTINUED)
PRIMARY
HPI control inputs. The HCNTL0 and HCNTL1 values between HPIA, and HPID registers
duringHPI reads and writes. These signals are only used in HPI multiplexed address/data
mode (HMODE pin is low).
These pins are shared with the external memory interface and are only used by the HPI
when the interface is in HPI mode (XIO pin is low).
HCNTL0
HCNTL1
PPA3
PPA2
I
I
O
O
Address strobe input. Hosts with multiplexed address and data pins require HAS to latch
the address in the HPIA register. This signal is only used in HPI multiplexed address/data
mode (HMODE pin is low).
‡§
HAS
‡§
PPA4
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
HPI chip-select signal. Thissignal must be active during HPI transfers, and can remain
active between concurrent transfers.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
‡§
‡§
MSTRB
HCS
I
I
I
O
O
O
HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes to control
transfer HPI transfers.
These pins are shared with the external memory interface and are only used by the HPI
when the interface is in HPI mode (XIO pin is low).
‡§
HDS1
‡§
HDS2
‡§
PS
‡§
DS
HPI read/write signal. This signal is used by the host to control the direction of an HPI
transfer.
This pin is shared with the external memory interface and is only used by the HPI when
the interface is in HPI mode (XIO pin is low).
HR/W
R/W
HPI data-ready output. The ready output informs the host when the HPI is ready for the
next transfer.
This pin is shared with the external memory interface and is only used by the HPI when
theinterfaceisinHPImode(XIOpinislow).HRDYisplacedintothehigh-impedancestate
when OFF is low.
HRDY
O
READY
I
Host interrupt pin. HPI can interrupt the host by asserting this low. The host can clear this
interrupt by writing a “1” to the HINT bit of the HPIC register. Only supported in HPI
multiplexed address/data mode (HMODE pin is low). These pins are placed into the
high-impedance state when OFF is low.
A_HINT
B_HINT
PPA0
PPA1
O
I
O
§
HPIRS
Host-port interface (HPI) reset pin. This signal resets the host port interface and both subsystems.
Host mode select. When this pin is low it selects the HPI multiplexed address/data mode. The multiplexed
address/data mode allows hosts with multiplexed address/data lines access to the HPI registers HPIC, HPIA,
and HPID. Host-to-DSP and DSP-to-host interrupts are supported in this mode.
HMODE
I
When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts with
separateaddress/data buses to access the HPI address range by way of the 18-bit address bus and the HPI data
(HPID) register via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not supported in this mode.
SUPPLY PINS
AV
DD
S
S
S
S
Dedicated power supply that powers the PLL. AV
DD
= 1.8 V. AV
can be connected to CV .
DD
DD
CV
DV
Dedicated power supply that powers the core CPUs. CV
DD
= 1.8 V
DD
DD
Dedicated power supply that powers the I/O pins. DV
DD
= 3.3 V
V
SS
Digital ground. Dedicated ground plane for the device.
†
‡
§
¶
#
||
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
This pin is used by Texas Instruments for device testing and should be left unconnected.
This pin has an internal pulldown resistor.
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