TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
SUPPLY PINS (CONTINUED)
Analog ground. Dedicated ground for the PLL. V
not separated.
can be connected to V
if digital and analog grounds are
SS
SSA
V
SSA
S
TEST PIN
#
TEST
No connection
EMULATION/TEST PINS
Standard test clock. This is normally a free-running clock signal with a 50% duty cycle. Changes on the test
access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or
selectedtest-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling
edge of TCK.
‡§
TCK
I
Test data input. Pin with an internal pullup device. TDI is clocked into the selected register (instruction or data)
on a rising edge of TCK.
‡
TDI
TDO
TMS
I
O
I
Test data pin. The contents of the selected register is shifted out of TDO on the falling edge of TCK. TDO is in
high-impedance state except when the scanning of data is in progress. These pins are placed into high-im-
pedance state when OFF is low.
Test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on
the rising edge of TCK.
‡
Test reset. When high, TRST gives the scan system control of the operations of the device. If TRST is driven low,
the device operates in its functional mode and the emulation signals are ignored. Pin with internal pulldown
device.
||
TRST
I
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined
as I/O.
EMU0
I/O/Z
Emulator interrupt 1 pin. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator
system and is defined as I/O. When TRST transitions from high to low, then EMU1 operates as OFF. EMU/OFF
= 0 puts all output drivers into the high-impedance state.
EMU1/OFF
I/O/Z
Note that OFF is used exclusively for testing and emulation purposes (and not for multiprocessing applications).
Therefore, for the OFF condition, the following conditions apply:
TRST = 0, EMU0 = 1, EMU1 = 0
†
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
This pin is used by Texas Instruments for device testing and should be left unconnected.
This pin has an internal pulldown resistor.
‡
§
¶
#
||
14
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