TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
sequential EMIF
The sequential EMIF option allows one master subsystem to run from external memory while controlling the
slave subsystem’s RS signal and the SELA/B pin. At system reset, only the master subsystem is actually reset.
Upon a low-to-high transition of the master’s RS signal, the master subsystem fetches the reset vector and
proceeds to copy external application code to internal memory space. The master subsystem begins executing
the application code, then changes the state of SELA/B, relinquishing the external EMIF to the slave subsystem.
The master then releases the slave RS signal. As a result, the slave fetches the reset vector and begins to copy
the external application code to internal memory space. Note, GPIO pins on the master subsystem can be used
to control the SELA/B and slave reset (x_RS) pins externally.
on-chip peripherals
All the ’54x devices have the same CPU structure; however, they have different on-chip peripherals connected
to their CPUs. The on-chip peripheral options provided on each subsystem of the ’5420 are:
D
D
D
D
D
D
Software-programmable wait-state generator
Programmable bank-switching
16-bit host-port interface (HPI16)
Multichannel buffered serial ports (McBSPs)
A hardware timer
A software-programmable clock generator with a phase-locked loop (PLL)
software-programmable wait-state generators
The Software-programmable wait-state generator can be used to extend external bus cycles up to fourteen
machine cycles to interface with slower off-chip memory and I/O devices. Note that all external memory
accesses on the ’5420 require at least one wait state. The software wait-state register (SWWSR) controls the
operation of the wait-state generator. The SWWSR of a particular DSP subsystem (A or B) is used for the
external memory interface, depending on the logic level of the SELA/B pin.The 14 LSBs of the SWWSR specify
the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges.
This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
definesamultiplicationfactorof1or2forthenumberofwaitstates. Atreset, thewait-stategeneratorisinitialized
to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3
and described in Table 2.
15
14
12 11
9
8
6
5
3
2
0
XPA
I/O
R/W-111
Data
R/W-111
Data
Program
R/W-111
Program
R/W-111
R/W-0
R/W-111
LEGEND: R=Read, W=Write, 0=Value after reset
Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
