TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
functional overview
P, C, D, E Buses and Control Signals
36K
Program
SARAM
48K Prog/Data
SARAM
16K Prog/Data
DARAM
’C54x Core A
DMA Bus
GPIO[3:0]
McBSP0
Peripheral
Bus
Bridge
Peripheral Bus
CPU BUS
McBSP1
McBSP2
Modified HPI16
Host Access Bus
DMA
(6 channels)
TIMER
APLL
JTAG
Clocks
DSP Subsystem A
Core-to-Core
FIFO Interface
Interprocessor IRQ’s
P, C, D, E Buses and Control Signals
36K
Program
SARAM
48K Prog/Data
SARAM
16K Prog/Data
DARAM
’C54x Core B
DMA Bus
GPIO[3:0]
McBSP0
Peripheral
Bus
Bridge
Peripheral Bus
CPU Bus
McBSP1
McBSP2
Modified HPI16
Host Access Bus
DMA
(6 channels)
TIMER
JTAG
DSP Subsystem B
Figure 1. Functional Block Diagram
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