TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
reset vectorinitialization (continued)
Theselectionoftheresetinitializationoptionisdeterminedbythestateofthreepins;XIO, XMODE, andSELA/B.
The options include:
D
D
D
D
HPI (host-dependent)
EMIF-to-HPI (stand-alone)
Simultaneous EMIF (stand-alone)
Sequential EMIF (stand-alone)
HPI
The HPI method is only valid when the level of the XIO pin is low. The ’5420 acts as a slave to an external master
host. The host device must keep the ’5420 device in reset as it downloads code to the subsystem that is
determined by the logic level of the SELA/B pin. When SELA/B is low, the master downloads code to
subsystem A. By driving SELA/B high, the master host can subsequently download code to subsystem B. The
HMODE pin determines the configuration of the HPI (multiplexed or nonmultiplexed) and is an asynchronous
input. Therefore, HMODE can be changed to the desired configuration while A_RS and B_RS are low prior to
the transfer. Once the subsystem(s) have been loaded and are ready to execute, the master host can release
the reset pin(s).
There are two valid options for controlling the reset function of the subsystems. The first option is to hold the
A_RS and B_RS pins low while the HPIRS pin transitions from low to high. This keeps the cores in reset while
allowing the HPI full access to download the application code. The host can now drive the A_RS and B_RS
signalshigh simultaneously or separately to release the respective subsystem from reset. The subsystems then
fetch their respective reset vector. If the subsystems are released from reset seperately, subsystem A should
be released from reset first, since the A_RS pin resets the on-chip PLL that is common to both subsystems.
Another valid option is to keep the A_RS and B_RS pins high while the host transitions the HPIRS pin from low
to high. Special internal logic causes the HPI to be fully operable and the cores remain in reset. As a result, after
the host processor has downloaded the application code via the HPI, it must perform an additional HPI write
(any value) to address 0x2F. This releases the respective subsystem from reset. By changing the value of
SELA/B, the host can write to 0x2F via the HPI to release the other subsystem from reset.
EMIF-to-HPI
In this particular vector initialization method, the host processor controlling the HPI is one of the subsystems.
The master host is subsystem A if SELA/B is low and subsystem B when SELA/B is high. As described in the
signal descriptions table, the address, data, and control signals of the program space are multiplexed with the
HPI signals. In a special mode when XIO is high (EMIF mode) and HMODE is high (HPI nonmultiplexed mode),
these multiplexed signals are connected, making it possible for the master subsystem’s EMIF to initialize the
slave subsystem via the slave’s HPI. The master subsystem then releases the slave from reset either by
transitioning the hardware reset signal (x_RS) high, or in software, by writing to memory location 0x2F via the
HPI. As a result, the slave core fetches the reset vector.
simultaneous EMIF
The simultaneous EMIF vector initialization option allows both subsystems to access external memory
simultaneously. The subsystems are designed to operate synchronized with one another while accessing the
same locations simultaneously. In this mode, when XIO is high and HMODE is low, one subsystem is given full
control of the EMIF while the other subsystem relies on the synchronization of the two subsystems. Instructions
fetched by one subsystem are ready for both subsystems to execute. After the application code is executed or
transferred to internal memory, write accesses to external memory are prohibited.
This method requires the A_RS and B_RS pins to be tied high while HPIRS transitions from low to high. When
HPIRS transitions high, both subsystems fetches the same reset vector.
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