TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
memory map
Hex
Data
Hex
Program Page 0
Hex
Program Page 1
Hex
Program Page 2
Hex
Program Page 3
Hex
I/O
0000
0000
10000
20000
30000
0000
Memory-
Mapped
Registers
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
DARAM 0
(16K Words)
Prog/Data
(OVLY=1)
005F
0060
Scratch-Pad
DARAM
007F
0080
On-Chip
DARAM 0
(16K Words)
External
(OVLY=0)
External
(OVLY=0)
External
(OVLY=0)
External
(OVLY=0)
†
†
†
†
3FFF
4000
3FFF
4000
13FFF
14000
23FFF
24000
33FFF
34000
On-Chip
On-Chip
On-Chip
On-Chip
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
SARAM 1
(16K Words)
Prog/Data
(OVLY=1)
On-Chip
SARAM 1
(16K Words)
64K
External
I/O Ports
†
External
(OVLY=0)
External
(OVLY=0)
External
(OVLY=0)
External
†
†
†
†
(OVLY=0)
7FFF
8000
7FFF
8000
17FFF
18000
27FFF
28000
37FFF
38000
Reserved
(MP/MC=0)
On-Chip
SARAM 2
(32K Words)
Prog/Data
(DROM=1)
On-Chip
On-Chip
External
(MP/MC=1)
SARAM 2
(32K Words)
Prog/Data
SARAM 3
(32KWords)
(MP/MC=0)
†
2EFFF
2F000
Reserved
(MP/MC=0)
On-Chip
SARAM 4
(4K Words)
(MP/MC=0)
(MP/MC=0)
External
(MP/MC=1)
†
External
(MP/MC=1)
External
External
(DROM=0)
†
†
(MP/MC=1)
†
External
(MP/MC=1)
†
FFFF
FFFF
1FFFF
2FFFF
3FFFF
FFFF
(extended)
(extended)
(extended)
(extended)
†
The external memory interface must be enabled by driving the XIO pin high, in order for external memory accesses to occur.
Figure 2. Memory Map for Each CPU Subsystem
multicore reset signals
The ’5420 device includes three reset signals: A_RS, B_RS, and HPIRS. The A_RS and B_RS pins function
as the CPU reset signal for subsystem A and subsystem B, respectively. These signals reset the state of the
CPU registers and upon release, initiates the reset function. Additionally, the A_RS signal resets the on-chip
PLL and initializes the CLKMD register to bypass mode.
The HPI reset signal (HPIRS) places the HPI peripheral into a reset state. It is necessary to wait three clock
cycles after the rising edge of HPIRS before performing an HPI access.
reset vector initialization
The ’5420 device does not have on-chip ROM and therefore does not contain bootloader routines/software.
Consequently, the user must have a valid reset vector in place before releasing the reset signal. This is referred
to as reset vector initialization. After reset, the ’5420 device fetches the reset vector at address 0xFF80 in
program memory and begins to execute the instructions found in memory. The application code is raw program
and data words and does not require the traditional boot-table or boot-packet format.
18
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