TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
Signal Descriptions (Continued)
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NAME
TYPE
DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS (CONTINUED)
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A_BCLKX0
B_BCLKX0
A_BCLKX1
B_BCLKX1
A_BCLKX2
B_BCLKX2
Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be configured as
an input by setting the CLKXM = 0 in the PCR register. BCLKX can be sampled as an input by way of the IN1
bit in the SPC register. When not being used as a clock, these pins can be used as general-purpose I/O by setting
XIOEN = 1.
I/O/Z
These pins are placed into the high-impedance state when OFF is low.
A_BDR0
B_BDR0
A_BDR1
B_BDR1
A_BDR2
B_BDR2
Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can be used as
general-purpose I/O by setting RIOEN = 1.
I
A_BDX0
B_BDX0
A_BDX1
B_BDX1
A_BDX2
B_BDX2
Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins can be used as
general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF is
low.
O/Z
A_BFSR0
B_BFSR0
A_BFSR1
B_BFSR1
A_BFSR2
B_BFSR2
Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the receive-data process
over BDR pin. When not being used as data-receive synchronization pins, these pins can be used as
general-purpose I/O by setting RIOEN = 1.
I/O/Z
I/O/Z
A_BFSX0
B_BFSX0
A_BFSX1
B_BFSX1
A_BFSX2
B_BFSX2
Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the transmit-data
process over BDX pin. If RS is asserted when BFSX is configured as output, then BFSX is turned into input mode
by the reset operation. When not being used as data-transmit synchronization pins, these pins can be used as
general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state when OFF is
low.
HOST-PORT INTERFACE SIGNALS
HPI address inputs. HA[0:17] are used by the host device, in the HPI non-multiplexed
mode (HMODE pin is high), to address the on-chip RAM of the ’5420. These pins are
sharedwiththeexternalmemoryinterfaceandareonlyusedbytheHPIwhentheinterface
PRIMARY
HA[0:17]
HD[0:15]
I
PPA[0:17]
O
is in HPI mode (XIO pin is low).
Parallel bidirectional data bus. HD[0:15] are used by the host device to transfer data to
and from the on-chip RAM of the ’5420. These pins are shared with the external memory
interface and are only used by the HPI when the interface is in HPI mode (XIO pin is low).
Thedatabusincludesbusholderstoreducepowerdissipationcausedbyfloating, unused
pins. The bus holders also eliminate the need for external pullup resistors on unused pins.
When the data bus is not being driven by the ’5420, the bus holders keep data pins at the
last driven logic level. The data bus keepers are disabled at reset and can be
enabled/disabled via the BH bit of the BSCR register. These pins are placed into the
high-impedance state when OFF is low.
I/O/Z
I/O/Z
PPD[0:15]
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I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
This pin is used by Texas Instruments for device testing and should be left unconnected.
This pin has an internal pulldown resistor.
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