TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
§
§
A_RS
B_RS
I
The XIO pin is used to configure the parallel port as a host-port interface (HPI mode when XIO pin is low), or as
an asynchronous memory interface (EMIF mode when XIO pin is high).
XIO
I
At device reset, the logic combination of the XIO, HMODE, and SELA/B pin levels determines the initialization
value of the MP/MC bit (a bit in the processor mode status (PMST) register ) Refer to the memory section for
details.
GENERAL-PURPOSE I/O SIGNALS
A_XF
B_XF
External flag output (latched software-programmable output-only signal). Bit addressable. A_XF and B_XF are
placed into the high-impedance state when OFF is low.
O
A_GPIO0
B_GPIO0
A_GPIO1
B_GPIO1
General-purpose I/O pins (software-programmable I/O signal). Values can be latched (output) by writing into the
GPIO register. The states of GPIO pins (inputs) can be read by reading the GPIO register. The GPIO direction
is also programmable by way of the DIRn field in the GPIO register.
I/O
General-purpose I/O. These pins can be configured in the same manner as GPIO0–1; however in input mode,
the pins also operate as the traditional branch control bit (BIO). If application code does not perform
BIO-conditional instructions, these pins operate as general inputs.
A_GPIO2/BIO
B_GPIO2/BIO
PRIMARY
When the device is in HPI mode and HMODE = 0 (multiplexed), these pins are controlled
A_GPIO3
(A_TOUT)
by the general-purpose I/O control register. TOUT bit must be set to “1” to drive the timer
output on the pin. IF TOUT = 0, then these pins are general-purpose I/Os. In EMIF mode
(XIO pin high), these signals serve their primary functions and are active during external
I/O space accesses.
IOSTRB
I/O
O
B_GPIO3
(B_TOUT)
IS
MEMORY CONTROL SIGNALS
Program space select signal. The PS signal is asserted during external program space accesses. This pin is
placed into the high-impedance state when OFF is low.
‡
PS
O
O
This pin is also multiplexed with the HPI, and functions as the HDS1 data strobe input signal in HPI mode. Refer
to the HPI section of this table for details on the secondary function of this pin.
Data space select signal. The DS signal is asserted during external data space accesses. This pin is placed into
the high-impedance state when OFF is low.
‡
DS
This pin is also multiplexed with the HPI, and functions as the HDS2 data strobe input signal in HPI mode. Refer
to the HPI section of this table for details on the secondary function of this pin.
I/O space select signal. The IS signal is asserted during external I/O space accesses. This pin is placed into the
high-impedance state when OFF is low.
IS
O
O
This pin is also multiplexed with the general purpose I/O feature, and functions as the B_GPIO3 (B_TOUT)
input/outputsignalinHPImode. RefertotheGeneralPurposeI/Osectionofthistablefordetailsonthesecondary
function of this pin.
Program and data memory strobe (active in EMIF mode). This pin is placed into the high-impedance state when
OFF is low.
‡§
MSTRB
†
‡
§
¶
#
||
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register in subchip A.
This pin is used by Texas Instruments for device testing and should be left unconnected.
This pin has an internal pulldown resistor.
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