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TMS320VC5407 参数 Datasheet PDF下载

TMS320VC5407图片预览
型号: TMS320VC5407
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications  
5.11 Reset, BIO, Interrupt, and MP/MC Timings  
Table 518 assumes testing over recommended operating conditions and H = 0.5t  
Figure 516, and Figure 517).  
(see Figure 515,  
c(CO)  
Table 518. Reset, BIO, Interrupt, and MP/MC Timing Requirements  
MIN  
3
MAX  
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low  
Hold time, BIO after CLKOUT low  
h(RS)  
4
h(BIO)  
Hold time, INTn, NMI, after CLKOUT low  
1
h(INT)  
Hold time, MP/MC after CLKOUT low  
4
h(MPMC)  
w(RSL)  
‡§  
Pulse duration, RS low  
4H+3  
2H+3  
4H  
Pulse duration, BIO low, synchronous  
w(BIO)S  
w(BIO)A  
w(INTH)S  
w(INTH)A  
w(INTL)S  
w(INTL)A  
w(INTL)WKP  
su(RS)  
Pulse duration, BIO low, asynchronous  
Pulse duration, INTn, NMI high (synchronous)  
Pulse duration, INTn, NMI high (asynchronous)  
Pulse duration, INTn, NMI low (synchronous)  
Pulse duration, INTn, NMI low (asynchronous)  
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup  
2H+2  
4H  
2H+2  
4H  
8
Setup time, RS before X2/CLKIN low  
3
Setup time, BIO before CLKOUT low  
7
su(BIO)  
Setup time, INTn, NMI, RS before CLKOUT low  
Setup time, MP/MC before CLKOUT low  
7
su(INT)  
5
su(MPMC)  
The external interrupts (INT0INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs  
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 100 sequence at the timing that is  
corresponding to three CLKOUTs sampling sequence.  
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization  
and lock-in of the PLL.  
§
Note that RS may cause a change in clock frequency, therefore changing the value of H.  
The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).  
X2/CLKIN  
t
su(RS)  
t
w(RSL)  
RS, INTn, NMI  
CLKOUT  
BIO  
t
su(INT)  
t
h(RS)  
t
su(BIO)  
t
h(BIO)  
t
w(BIO)S  
Figure 515. Reset and BIO Timings  
88  
SPRS007D  
November 2001 Revised April 2004