Electrical Specifications
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MCSL)
t
d(MCSH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5−10. Memory Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
Wait
States
States
Generated
by READY
Trailing
Cycle
Generated
Internally
Figure 5−11. Memory Write With Externally Generated Wait States
85
November 2001 − Revised April 2004
SPRS007D
TI [ TEXAS INSTRUMENTS ]
