Electrical Specifications
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5−12. I/O Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
Trailing
Cycle
States
Wait
Generated
Internally
States
Generated
by READY
Figure 5−13. I/O Write With Externally Generated Wait States
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SPRS007D
November 2001 − Revised April 2004