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TMS320VC5407 参数 Datasheet PDF下载

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型号: TMS320VC5407
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications  
5.9 Ready Timing for Externally Generated Wait States  
Table 514 and Table 515 assume testing over recommended operating conditions and H = 0.5t  
Figure 510, Figure 511, Figure 512, and Figure 513).  
(see  
c(CO)  
Table 514. Ready Timing Requirements for Externally Generated Wait States  
MIN  
7
MAX  
UNIT  
t
t
t
t
t
t
Setup time, READY before CLKOUT low  
Hold time, READY after CLKOUT low  
ns  
ns  
ns  
ns  
ns  
ns  
su(RDY)  
0
h(RDY)  
Valid time, READY after MSTRB low  
4H 4  
4H 4  
v(RDY)MSTRB  
h(RDY)MSTRB  
v(RDY)IOSTRB  
h(RDY)IOSTRB  
Hold time, READY after MSTRB low  
4H  
Valid time, READY after IOSTRB low  
Hold time, READY after IOSTRB low  
4H  
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,  
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.  
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.  
Table 515. Ready Switching Characteristics for Externally Generated Wait States  
PARAMETER  
Delay time, MSC low to CLKOUT low  
Delay time, CLKOUT low to MSC high  
MIN  
1  
1  
MAX  
UNIT  
ns  
t
4
d(MSCL)  
t
4
ns  
d(MSCH)  
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,  
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.  
84  
SPRS007D  
November 2001 Revised April 2004  
 
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