Electrical Specifications
5.9 Ready Timing for Externally Generated Wait States
Table 5−14 and Table 5−15 assume testing over recommended operating conditions and H = 0.5t
Figure 5−10, Figure 5−11, Figure 5−12, and Figure 5−13).
(see
c(CO)
†
Table 5−14. Ready Timing Requirements for Externally Generated Wait States
MIN
7
MAX
UNIT
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
ns
ns
ns
ns
ns
ns
su(RDY)
0
h(RDY)
‡
Valid time, READY after MSTRB low
4H − 4
4H − 4
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after MSTRB low
4H
‡
Valid time, READY after IOSTRB low
‡
Hold time, READY after IOSTRB low
4H
†
‡
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
†
Table 5−15. Ready Switching Characteristics for Externally Generated Wait States
PARAMETER
Delay time, MSC low to CLKOUT low
Delay time, CLKOUT low to MSC high
MIN
− 1
− 1
MAX
UNIT
ns
t
4
d(MSCL)
t
4
ns
d(MSCH)
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
84
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
