Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timing
5.14.1 McBSP Transmit and Receive Timings
Table 5−21 and Table 5−22 assume testing over recommended operating conditions (see Figure 5−21 and
Figure 5−22).
†
Table 5−21. McBSP Transmit and Receive Timing Requirements
MIN
MAX
UNIT
ns
‡
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
4P
c(BCKRX)
‡
Pulse duration, BCLKR/X high or BCLKR/X low
2P−1
ns
w(BCKRX)
8
1
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
1
2
7
1
2
Hold time, BDR valid after BCLKR low
3
10
1
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
0
2
t
t
Rise time, BCKR/X
Fall time, BCKR/X
6
6
ns
ns
r(BCKRX)
f(BCKRX)
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 0.5 * processor clock
92
SPRS007D
November 2001 − Revised April 2004
TI [ TEXAS INSTRUMENTS ]
